The invention lies in the field of semiconductors. The invention relates to an integrated semiconductor circuit with a protective structure for protection against electrostatic discharge.
Semiconductor circuits integrated in a chip contain protective circuits for protecting the inputs or outputs (I/O ports) against electrostatic overvoltages and electrostatic discharges (ESD). The ESD protective elements are connected between the input pad of an integrated semiconductor circuit and the input or output terminal to be protected. Consequently, the ESD protective elements ensure that when a parasitic overvoltage is coupled, the in ESD element is turned on and the parasitic overvoltage pulse is conducted away to one of the supply voltage conductive tracks. Such overvoltage pulses can lead, in the extreme case, to the destruction of the component. An ESD protective element is disclosed in European Patent Application 0 414 934 A1.
Under operating conditions described, for example, in a product specification, the ESD protective elements must not adversely affect the function of the integrated semiconductor circuits to be protected. In other words, the turn-on voltage of the ESD protective elements must lie outside the signal voltage range of the protected terminal pads. In order to develop a good protective action, the ESD protective element should break down before the most critical circuit path. As a rule, proper break down requires an exact setting of the turn-on voltage of the respective ESD protective elements with the essential boundary condition that the process control (which has been optimized with regard to the properties of the components of the integrated semiconductor circuit to be protected) is not altered by the insertion of the ESD protective elements.
A further essential boundary condition results from the spatial configuration of the terminal pads in immediate proximity to the integrated semiconductor circuit to be protected. In particular, the terminal pads are disposed in the vicinity of the output drives due to the relatively high currents to be driven. The ESD protective structure is, therefore, frequently connected to that supply line from which the output driver is supplied.
What is essential to the functioning of generic type ESD protective elements is the capability of allowing short high-current pulses right into the ampere range to be conducted away without the ESD element being damaged by the high-current pulses. The protective elements are operated in the event of breakdown during the ESD pulse. Because the protective elements have to be provided at all supply and signal terminals, they must be configured to be as compact and space-saving as possible. At the same time, the current to be conducted away must be distributed as uniformly as possible over the entire breakdown path. Uniform distribution obtains the highest possible total current through the protective element and, hence, a high ESD strength up to a critical current density that can lead to damage to the protective element (second breakdown).
Particularly, in the case of protective elements having a snapback behavior of the characteristic curve in the event of breakdown (e.g. bipolar transistors or thyristors), there is a risk that a location on the breakdown path or a finger of a multifinger structure triggers and conducts away the current without the remaining regions of the breakdown structure or the remaining fingers turning on. The protective elements and the integrated circuits to be protected that are connected downstream are often destroyed as a result of the effect.
Occasionally, very large potential differences in the base zone of the protective elements are the cause of such an inhomogeneous turn-on. These potential differences result from the very high sheet resistance of the base and the high currents to be conducted away. As a rule, an improvement can be obtained only by a suitable metallic interconnection of the base regions, in particular, finger structures. However, such interconnection requires contact to be made with the base regions, such contact being associated with a high outlay in terms of area. Moreover, the degree of homogenization that can be attained will differ greatly depending on configuration stipulations and technological parameters.
With regard to further details, features, advantages and method of operation of the ESD protective circuits, European Patent Applications 0 623 958 A1 and 0 414 934 A1 are incorporated by reference.
It is accordingly an object of the invention to provide an integrated semiconductor circuit with a protective structure for protection against electrostatic discharge that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that provides an ESD protective structure that has a distinctly improved homogenization of the current flow in the event of breakdown.
With the foregoing and other objects in view, there is provided, in accordance with the invention, in a semiconductor assembly having at least one semiconductor body, an integrated semiconductor circuit disposed in the at least one semiconductor body, an electrically conductive connecting line, at least one terminal pad connected to the integrated semiconductor circuit through the connecting line, at least one first busbar carrying a first supply potential of the integrated semiconductor circuit during operation, at least one second busbar carrying a second supply potential of the integrated semiconductor circuit during operation, and a protector for protecting the integrated semiconductor circuit against electrostatic discharge, the protector disposed between the at least one terminal pad and the integrated semiconductor circuit and connected to at least one of the at least one first busbar and the at least one second busbar, the protector including at least one protective element having first transistors each having a base terminal, a collector terminal, and majority charge carriers of a first conduction type, second transistors each having a base terminal, a collector terminal, and majority charge carriers of a second conduction type, the first transistors and the second transistors respectively connected by reciprocal coupling of at least one of the base terminals and the collector terminals to form a thyristor structure, at least one first integrated resistor with a lowest possible resistance driving the base terminals of the second transistors and the collector terminals of the first transistors, and a buried layer having partial regions with a higher doping concentration than regions of the buried layer outside the partial regions.
Integrated vertical switching transistors are utilized as ESD protective elements. The bases of the switching transistors are driven by integrated driving transistors. Essentially, the current gain (base-collector gain) of the driving transistors is small enough to avoid the triggering of the parasitic thyristorxe2x80x94which results from the wiring of the switching transistors and of the driving transistorsxe2x80x94with an undesirable snapback of the high-current characteristic curve at the sustaining voltage. The turn-on voltage of the ESD protective element can be established advantageously by a suitable selection of the base widths of the driving transistors.
A buried layer configured to have the lowest possible resistance is essential to the invention. The sheet resistance of the buried layer defines an integrated resistor that is disposed between the base terminals of the driving transistors and the collector terminals of the switching transistors, and which enables homogenization of the current flow in the event of breakdown.
In accordance with another feature of the invention, the partial regions are disposed next to one another and/or are spaced apart from one another in the buried layer.
In accordance with an additional feature of the invention, there is provided a further partial region having at least one base zone, at least one first emitter zone, and at least one second emitter zone, and wherein the at least one protective element is disposed in the further partial region, the first transistors are switching transistors, the second transistors are driving transistors, the at least one base zone is a well, has the first conduction type, and forms the base terminals of the switching transistors and the collector terminals of the driving transistors, the at least one first emitter zone is a well, has the second conduction type, is disposed in the at least one base zone and forms the emitter terminals of the switching transistors, and the at least one second emitter zone is a well, has the first conduction type, is spaced apart from the at least one base zone by a first distance, and forms the emitter terminals of the driving transistors.
In accordance with yet another feature of the invention, the at least one first emitter zone forms the emitter terminals of every one of the switching transistors.
In accordance with yet a further feature of the invention, the buried layer is at least one buried layer, and the at least one buried layer has the second conduction type and the first integrated resistor and forms the collector terminals of the first transistors and the base terminals of the second transistors.
In accordance with yet an added feature of the invention, the at least one buried layer has a doping concentration, and a conductance of the first integrated resistor is defined by the doping concentration of the at least one buried layer.
In accordance with yet an additional feature of the invention, the first transistors are switching transistors and the second transistors are driving transistors for driving the switching transistors.
In accordance with again another feature of the invention, the switching transistors have a base-collector gain, and the driving transistors have a base-collector gain significantly less than the base-collector gain of the switching transistors.
In accordance with again a further feature of the invention, the second transistors are driving transistors having a base-collector gain defined by the first distance.
The buried layer is connected to the terminal pad through a connection zone, which is doped as heavily as possible for reasons of good conductivity. The connection zone defines a partial region in which are disposed the protective elements. The partial region is typically disposed in an epitaxial layer. It is particularly advantageous if the connection zone is configured as a closed ring around the partial region.
In accordance with again an added feature of the invention, there is provided at least one connection zone connected to the buried layer and to at least one of the at least one first busbar and the at least one second busbar.
In accordance with still another feature of the invention, there are provided connection zones equidistantly spaced from at least one of the at least one base zone and the at least one second emitter zone by a second distance, and connected to the buried layer and to at least one of the at least one first busbar and the at least one second busbar
The connection zones are spaced equidistantly from the base zones and/or from the second emitter zones by a second distance. The second distance may typically be chosen to be sufficiently large that the parasitic bipolar transistor in the edge region of the partial zone does not turn on.
In accordance with still a further feature of the invention, the at least one connection zone has a doping concentration, and a second integrated resistor having a conductance set by the doping concentration of the at least one connection zone.
A second integrated resistor, by which it is possible to set the drive sensitivity of the driving transistors, is essentially dependent on the doping concentration in the connection zone. In addition, the second resistor also depends on contact resistances of the electrical connections.
In accordance with still an added feature of the invention, the connection zones have a doping concentration, and a second integrated resistor having a conductance set by the doping concentration of the connection zones.
In accordance with still an additional feature of the invention, the at least one connection zone is a closed ring around the further partial region.
In accordance with yet another feature of the invention, the connection zones form a closed ring around the further partial region.
In accordance with yet a further feature of the invention, the at least one connection zone and the further partial region define a given lateral cross-sectional area, and the buried layer has a lateral cross-sectional area larger than the given lateral cross-sectional area.
In accordance with yet an added feature of the invention, the connection zones and the further partial region define a given lateral cross-sectional area, and the buried layer has a lateral cross-sectional area larger than the given lateral cross-sectional area.
The lateral cross-sectional area of the buried layer is typically larger than the lateral cross-sectional area of the connection zone and of the partial region.
In accordance with yet an additional feature of the invention, the semiconductor body has an epitaxial layer and the further partial region is in the epitaxial layer of the semiconductor body.
The emitter zones typically have a significantly higher doping concentration than the base zones and/or the epitaxial layer. The doping concentration in the epitaxial layer is often defined by the process control for fabricating the integrated circuit.
The buried layer and the connection zones are very heavily doped in order to satisfy the requirements of a very high conductance. Typically, these zones have a doping concentration of more than 1*1019 cmxe2x88x923.
In accordance with yet another feature of the invention, the at least one first emitter zone has a higher doping concentration than the at least one base zone.
In accordance with a concomitant feature of the invention, the buried layer has a doping concentration greater than 1*1019 cm xe2x88x923.
The invention is particularly advantageous for use in a semiconductor memory or a logic component. A further advantageous application of the invention is for use in a microcontroller.
The invention is typically integrated in bipolar circuits. The switching transistor may be an npn bipolar transistor and the driving transistor may be a pnp bipolar transistor. It is particularly advantageous, however, if the integrated semiconductor circuit, and also the ESD protective element, are fabricated using CMOS technology, for example, the switching transistor is an n-channel MOSFET and the driving transistor is a p-channel MOSFET transistor.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor circuit with protective structure for protection against electrostatic discharge, it is nevertheless not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.